Sprout24 CPU
Sprout24 is a "know-your-roots" computer processor — designed and built from the ground up as a teaching tool to help introduce the basics of computer science and demystify how computers work.
early code execution test
We've heard that computers work entirely in ones and zeroes... but what does that even mean? How is that really enough to let modern computers, phones, and devices do all the amazing things that they can?
Let's take a look together at how that all works, using the design of the Sprout24 along the way to illustrate how simple pieces working together like an orchestra can make beautiful things possible.
Development is currently underway, having just reached a big milestone with the assembly and start of testing of the first complete CPU. A more complete public project launch is expected later in 2023, with plans to present it at Penguicon 2024. I'm looking forward to sharing more with you!
~ Autumn
November 21, 2023 — Testing is progressing much faster with the help of the new test interface. I've identified and worked around two hardware bugs this week — one was a clock skew issue that was allowing bad data to seep into general registers, and the other was from the IR input bus missing its pulldowns so the IR sometimes clocked garbage data during a memory-access stall cycle.
November 14, 2023 — Revised Northwest board is testing good. The backplane and test interface are working. Now to keep moving forward with extensive testing of the CPU as a whole. There is so much complexity to test, but the new test interface board will make it a lot easier than having to wire every bit of the test connections by hand.
November 7, 2023 — Backplane, debugger, and revised Northwest board have arrived.
October 30, 2023 — Placed order for the backplane, debugger, and revised Northwest board.
October 23, 2023 — Trying to debug everything is becoming more and more of a ratsnest of wires. I would eventually need to design a backplane anyway, so I just finished a basic 8-port backplane and am starting on a debugger expansion board that will interface between the backplane and a Raspberry Pi to drive the testing. The plan is to order the updated Northwest board, the backplane, and the debugger board in the same order to save on shipping.
October 13, 2023 — We had a lot of family adventures and outdoor fun over the summer. Now that it's cold outside again, I'm back to working on this project in the evenings. Tonight I created revision B of the Northwest board that fixes the lookahead carry for the PC and SP incrementors. I also updated this board from KiCAD 5 to KiCAD 7; it took a surprising amount of work to adjust for the changes that came from that.
Some quick highlights:
24-bit CPU
Load/store architecture
Word-addressing
RISC-style instruction set
53 instructions and interrupt support
Lightly pipelined
Working assembler and emulator
25 PCBs and 2,634 components
1,054 ICs, many of which are single logic gates
Approx. 9,700 total logic gates or 29,300 transistors
730 LEDs
Load/store architecture
Word-addressing
RISC-style instruction set
53 instructions and interrupt support
Lightly pipelined
Working assembler and emulator
25 PCBs and 2,634 components
1,054 ICs, many of which are single logic gates
Approx. 9,700 total logic gates or 29,300 transistors
730 LEDs
I did find a design oops on the carry-lookahead adder that increments the program counter, so it goes haywire after counting to 256, but I think I will be able to bodge that to be able to finish testing.
April 4, 2023 — All boards are tested as well as they can be individually. Tonight I assembled all the boards together, and she's beautiful. I'll be powering the whole thing up and starting to test it in the coming days.
April 1, 2023 — Assembled ALU and Register 01 boards are complete and match emulator in testing. Register File and Control Unit are complete and pass spot-check testing.
March 30, 2023 — The order is in, and all 25 boards that make up the CPU are ready to test and assemble!
March 8, 2023 — Placed order for all remaining CPU boards, including the Southeast and East Bridge boards. Now we wait.
March 3, 2023 — My bank flagged the PCB order as suspicious, so I had to call them to confirm it was legit. In the meantime I noticed an omission in the Register File board, so I put the order on hold and made a revision B for the Register File and West Bridge boards. At this point, I'm close enough on the layout of the Southeast board that I'm going to wait to try the order again until I can include the Southeast and East Bridge boards too.
February 28, 2023 — The Register File, Register 01, Northwest, and West Bridge board designs are now finished, and I just placed an order for those plus the Control Unit and ALU Core boards. There will be a lot of things to test once this order shows up.
February 1, 2023 — The Control Unit and ALU Core boards are ready to order, though I'm going to wait until I have a couple others ready to save on shipping costs.
Next to design are the "Northwest" board that includes components related to the program counter and stack pointer, and the "Southeast" board that relates to the instruction and status registers.
And I now have a tentative physical layout for how the individual boards will fit together into a complete CPU. Two additional helper boards with no components will sit below the rest of the boards for physical support and for routing busses between the boards above.
December 22, 2022 — The CPU's Control Unit is working and tested in the emulator, and now it's time to turn it into hardware. More details and a demo in this video.
November 22, 2021 — Ordered ALU Adder, ALU Logic, ALU Shifter, ShiftBusRead, ShiftBusWrite
October 2, 2021 — Ordered Register rev.B
March 1, 2020 — Ordered Register
February 5, 2020 — First KiCAD PCB sketch — for register board
September 27, 2019 — More design goals and ideas; sketches of board layouts
September 25, 2019 — Start of project notebook: description, what, why, first sketches of opcodes and isa, instruction encoding, register tower.
| cpu | |
|---|---|
| register | complete |
| register01 | complete |
| registerfile | may need rev b for clock issue |
| alu-core | complete |
| alu-adder | complete |
| alu-logic | complete |
| alu-shifter | complete |
| controlunit | complete |
| northwest | complete |
| southeast | revision B ordered |
| westbridge | complete |
| eastbridge | complete |
| extra-cpu boards | |
| backplane | complete, with bodge |
| backplane connector | ordered |
| ram | proof-of-concept w/sram good |
| rom | |
| isabridge | incomplete design sketch |
| shiftbus-read | complete |
| shiftbus-write | complete |
| test interface | complete |
| protocard | ordered |
| pinadapter | ordered |
| architecture | |
| instruction set | complete |
| emulator | working |
| assembler | working |
automated testing of completed alu
